Damascene refers to a process in which interconnect metal lines are delineated by isolating dielectrics. Damascening is not performed by lithography and etching, but by chemical-mechanical planarization (CMP). In damascening, an interconnect pattern is first lithographically defined in the layer of dielectric, and then metal is deposited to fill in the resulting trenches. Then excess metal is removed by means of chemical-mechanical polishing (planarization).
Chemical-mechanical polishing (CMP), also called chemical-mechanical planarization, refers to a method of removing layers of solid by chemical-mechanical polishing carried out for the purpose of surface planarization and definition of the metal interconnect pattern.
Dual damascene is a modified version of the damascene process that is used to form metal interconnect geometry using a CMP process instead of metal etching. In dual damascene, two interlayer dielectric patterning steps and one CMP step create a pattern that would otherwise require two patterning steps and two metal CMP steps when using a conventional damascene process.
FIG. 1(a) through FIG. 1(d) are drawings explaining a conventional method of manufacturing a semiconductor device having dual damascene structure wiring.
In a first conventional method of manufacturing a semiconductor shown in FIG. 1(a), a first silicon nitride (Si3N4) film 3, a first silicon oxide film 4, a second silicon nitride (Si3N4) film 5 and a second silicon oxide film 6 are successively formed over a layer insulation film 2 in which a first wiring layer 1 is embedded. The first wiring layers are formed on a substrate, not depicted in the drawings for the sake of brevity.
Next, as is shown in FIG. 1(b), anisotropic dry etching to open via hole 8 is performed using a first photoresist 7 as a mask. This etching is performed until the first nitride film 3 is exposed in the interior of via hole 8. The via hole 8 is also referred to as a contact hole. The first nitride film 3 acts as a stopper film that stops the progress of etching in this etching process as shown in FIG. 1(b).
When the etching to open via hole 8 is finished, the first photoresist 7 is removed from above the second silicon oxide film 6. Optionally, a second photoresist 9 that has an open portion that corresponds to the wiring slot 10 is formed in its place, as shown in FIG. 1(c).
Next, anisotropic dry etching to open wiring slot 10 is performed using the second photoresist 9 as a mask. This etching is performed under the condition that a silicon oxide film can be removed with a significant selection ratio to the silicon nitride film. At this time, the first silicon nitride film 3 and the second nitride film 5 are both used as stopper films that stop the progress of etching. Next, etching for the purpose of removing the second silicon nitride film 5 exposed in the bottom of wiring slot 10 and the first silicon nitride film 3 exposed in the bottom of via hole 8 is performed. If this processing is done properly, via hole 8 which exposes the surface of first wiring layer 1 and wiring slot 10 which leads to via hole 8 are formed as shown in FIG. 1(d).
A typical damascene structure according to the conventional art is described by D. Edeletein et al., Proc. IEEE IEDM (1997) and S. Venkatesan et al., Proc. IEEE IEDM (1997).
Via hole formation according to the conventional art gives rise to a number of problems as feature size decreases. For example, etch selectivity must be controlled during the etch to prevent photoresist from being prematurely removed to cause damage to the underlying layers. For example, if a plasma etch uses a gas mixture that contains a 1:1 proportion of oxygen to carbon monoxide, then both the photoresist and the material not covered by the photoresist would be etched at the same rate. In order to prevent damage to the semiconductor device, it would then be necessary to use a very thick layer of photoresist, which could then cause poor line, trench and via hole definition.
Additional difficulties in conventional etch processes arise when silicon is etched using a fluorocarbon gas such as CF4. The etch process converts the silicon to SiF4, but a polymeric carbon residue remains on the semiconductor, frequently appearing as a “fence” around the via hole.
As has been shown, the conventional art technologies have disadvantages arising from inefficient etching. These disadvantages give rise to manufacturing inefficiency, semiconductor damage and such phenomena as the creation of fences from residual materials around the via holes. These fences give rise to such unwanted effects such as parasitic capacitance and reduced conductance by the metal component. Accordingly there is a need to provide new etch technologies that minimize these disadvantageous phenomena.